1. Field of the Invention
The present invention generally relates to memory storage subsystems and more particularly relates to error detection techniques for digital memory.
2. Description of the Prior Art
The earliest large capacity memories for digital computers were electromechanical devices, such as magnetic storage drums. Because these were not truly random access devices and the average access time was so large, these were readily replaced with static magnetic memories. The most popular of these utilized small magnetic cores wherein each data bit was stored in the magnetic polarization of a different one of a large array of magnetic cores.
Magnetic memories have in large measure been replaced by monolithic semiconductors employing digital electronic circuits which store the data. In its simplest form, each data bit is stored in a different one of a large array of separate bistable circuits. Because accesses to semiconductor memories are completely electronic, they tend to have a very favorable cycle time when compared with magnetic memories. Historically, the major disadvantage of semiconductor memories was cost. However, current semiconductor fabrication technologies have made semiconductor memories extremely cost competitive.
Bipolar semiconductors provide the fastest memory devices. However, the much lower power dissipation of metal oxide semiconductors (i.e. MOS) has tended to make them the preferred choice for most general applications. The MOS technology requiring the least quiescent power (i.e. power required to maintain a static state when not switching) is complementary symmetry MOS (i.e. CMOS). This power saving becomes most prominent for large scale memories, as they tend to have a relatively larger number of cells in a quiescent state at any given time.
Currently, an extremely popular semiconductor memory architecture is the CMOS Static Random Access Memory (i.e. SRAM). The CMOS SRAM employs a complementary semiconductor pair as the basic storage element. In four transistor (i.e. 4T) CMOS SRAM cells, resistors are used to pull up the transistors of the bistable to the current source. The somewhat newer 6T cells employ two transistors rather than two resistors to provide the pull up function. A primary advantage of the 6T cells is that it is easier to fabricate pull up transistors than pull up resistors in a high density environment, particularly if random logic fabrication is also required.
All memory systems require two basic types of testing. The first such test type is functional. This is accomplished by writing known data into the memory and subsequently reading from the memory to see that the stored data is as expected. For most prior art memory systems, such testing is virtually the same. This is the case, because the memory function tends to be the same without regard to the actual storage technology.
The second test type is tailored to the specific memory technology employed. These tailored tests are needed because the failure modes of the different memory technologies are different. Kuo et al. discuss a tailored test methodology for 6T CMOS SRAM cells in "Soft-Defect Detection (SDD) Technique for a High-Reliability CMOS SRAM" IEEE Journal of Solid-State Circuits, Volume 25, No. 1, February 1990.
A primary disadvantage of most of these prior art testing techniques is that they preclude other system uses of the memory during the testing process. This results in an effective reduction in memory availability or memory bandwidth. This is particularly true in the Kuo et al. approach which performs circuit testing on each cell. Though various software and system techniques have been attempted which minimize this negative impact, the basic problem continues to exist.
An alternative and/or adjunct to memory testing is error correction. This approach does not impede memory availability or bandwidth, because it does not act until a failure has actually occurred. Perhaps the most prominent and most expensive error correction technique involves voting. In this approach, complete redundancy is employed to permit error detection at the time of memory access. Multiple redundant storage elements are employed to permit data recovery for high reliability applications. As with error correction techniques generally, voting does not test the memory for suitability of future use but rather attempts to mitigate the negative effects of a failure which has already occurred.